Please refer to FIG. 1, which is the block diagram of a conventional PLL frequency synthesizer. The conventional PLL frequency synthesizer 2 employs an external crystal oscillator (XO, e.g., a temperature compensated crystal oscillator: TCXO) 21 to generate an accurate reference signal, an on chip voltage controlled oscillator (VCO) 25 to generate a signal, a frequency divider 26 to divide the frequency of the signal by N, a phase frequency detector (PFD) 22 to compare the frequency divided signal with the reference signal, a charge pump (CP) 23 and a loop filter (LPF) 24 to adjust the oscillating frequency of the VCO 25. Due to the negative feedback scheme of the conventional PLL frequency synthesizer 2, the frequency of the output signal of the VCO FVCO will be stabilized at a product of an integer, N, and the frequency of the reference signal FTCXO. That is,FVCO=N·FTCXO  (1)
After the conventional phase locked loop (PLL) frequency synthesizer 2 locks the frequency of the output signal of the VCO 25, the jitter of the output signal of the VCO 25 will be decreased dramatically, and the phase noise within the frequency bandwidth of the PLL is suppressed, which could be observed from the frequency spectrum of the output signal of the VCO 25.
Since the frequency of the output signal of the conventional PLL frequency synthesizer 2 is an integer multiple, N, of the frequency of the reference signal, the configuration such as that of FIG. 1 is called the Integer-N PLL. There are many in conveniences regarding the design of the Integer-N PLL due to the unique feature that the frequency of the output signal is the integer multiples of the frequency of the reference signal. The frequency of the reference signal must be one of the same as the bandwidth and a factor of the bandwidth, and the locked time of the frequency is indirectly influenced by that (due to the consideration of stability, the loop bandwidth has to be less or equal to 1/10 of the frequency of the reference signal).
To solve this problem, another kind of PLL is developed, and is referred to as the Fractional-N PLL. In FIG. 2, the block diagram of a conventional Fractional-N PLL frequency synthesizer 3 is shown. The conventional Fractional-N PLL frequency synthesizer 3 further includes a PFFD 31, a modulator 32 and an adder 33 except for the components 21-25 of FIG. 1. An external integer modulus is employed, added with the output signal of the modulator, and the result thereof is input to the PFFD 31 to generate a modulus. The unique feature of this kind of Fractional-N PLL frequency synthesizer is that the output frequency of the VCO 25 is not an integer multiple of the reference signal anymore. That is,FVCO=N.F·FTCXO  (2)
In which, N is an integer, and F is a fraction that is less than one. The configuration of this kind of Fractional-N PLL frequency synthesizer 3 is different from that of the aforementioned Integer-N PLL frequency synthesizer 2 mainly because that an extra modulator 32 is included as shown in FIG. 2. In the process of phase locking, the modulator 32 will change the value of the modulus of the PFFD 31, and the average value of this modulus will be a predetermined non-integer value.
For example, if the modulus value of the PFFD 31 is set at 100 in four continuous time periods, and the modulus value of the PFFD 31 is set at 101 in another six continuous time periods, then the modulus value is equivalent to 100.6.
There are certain drawbacks regarding employing the configuration of this kind of Fractional-N PLL frequency synthesizer 3. From the above-mentioned descriptions, one could easily find that the modulus of the PFFD 31 is still an integer, but the continuous switching makes the modulus looks like a fraction. Thus, there are certain quantization errors in each of the output period. Using the aforementioned example to explain, the quantization error is 0.6 when the modulus is 100, the quantization error is 0.4 when the modulus is 101, these errors would make the Fractional-N PLL frequency synthesizer 3 generate extra phase noises and certain spurs, and someone provides a relatively more complex configuration of the modulator 32, e.g., a delta-sigma modulator (DSM), to make the module of the modulated signal randomized, which will move the energy of the quantization error to a place having a relatively higher frequency, and decrease the phase noises in the loop bandwidth. However, the problem raised before could not be solved since the PFFD 31 is an intrinsic integer frequency divider.
The function of the aforementioned PFFD 31 is to decrease the frequency of the output signal of the VCO 25 so as to compare with and to approach the frequency of the reference signal, and the principle of which is mainly based on counting the input signal to generate the output signal having a time period which is an integer multiple of the time period of the input signal.
FIG. 3 is the schematic circuit diagram of a conventional PFFD 31. In which, the PFFD 31 includes a plurality of 2/3 frequency dividers 311 electrically connected to each other in series and each having the integer moduli 2/3. The schematic circuit diagram of a conventional 2/3 frequency divider 311 is shown in FIG. 4. The 2/3 frequency divider 311 includes mainly two parts: the prescaler logic 3111 and the end-of-cycle logic 3112. The prescaler logic 3111 includes a first AND Gate 31111, a first latch 31112 and a second latch 31113 for processing the input signal, and the end-of-cycle logic 3112 includes a second AND Gate 31121, a third latch 31122, a third AND Gate 31123 and a fourth latch 31124 for determining the modulus of the frequency divider 311 according to the two modulus control signals MOD and FB_CTRL. Referring to FIG. 4, the feedback signal of the end-of-cycle logic 3112 will be maintained at logic 1 when one of the MOD and FB_CTRL is logic 0, the prescaler logic 3111 will not be influenced by that, the modulus is two, and the frequency of the input signal is divided by two. The feedback signal of the end-of-cycle logic 3112 will be maintained at logic 1 when both of the MOD and FB_CTRL are logic 1 such that the end-of-cycle logic 3112 will suppress the operation of the prescaler logic 3111 by one time period of the input signal, that is to say the frequency of the input signal is divided by three, and the modulus is three.
Please refer to FIG. 3 again, the 2/3 frequency divider 311 will divide the frequency of the input signal (FIN/FOUT1/ . . . FOUTN) by three only when both of the MOD (MOD0/MOD1/ . . . MODN) and the FB_CTRL (FB_CTRL1/FB_CTRL2 . . . /FB_CTRLN+1) of the same stage are logic 1. For each of the plurality of 2/3 frequency dividers 311 electrically connected to each other in series, the FB_CTRL is the CTRLOUT signal (as shown in FIG. 4) from the next stage, the FB_CTRL of the last stage of the plurality of 2/3 frequency dividers 311 is directly connected to logic 1, and the feedback signal of which will be changed from logic 0 to logic 1 each time when the output signal of the last stage of the plurality of 2/3 frequency dividers 311 is logic 1; if the MOD of the previous stage (MODN−1) is logic 1, the modulus of the previous stage (N) will be 3, otherwise, the modulus of the previous stage (N) will be 2; but no matter what value the MODN−1 is, the feedback signal of the last stage will also become logic 1 so as to control the modulus of the previous stage (N). Thus, the modulus of the whole plurality of 2/3 frequency dividers 311 electrically connected to each other in series can be derived accordingly as follow:TOUT=(2N+1+2N·*MODN+ . . . +22·MOD2+2·MOD1+MOD0)·TIN  (3)In which, TOUT is the time period of the output signal FOUT, and TIN is the time period of the input signal FIN From the above-mentioned formula, two main drawbacks are: (1) the modulus range is limited within 2N+1 to 2N+2−1 and (2) the adjustable step size is 1.
Keeping the drawbacks of the prior arts in mind, and employing experiments and research full-heartily and persistently, the configuration and the controlling method of the Fractional-N PLL having the fractional frequency divider are finally conceived by the applicants.